1. Field of the Invention
The present invention relates to a microcomputer having a function of communicating with other microcomputers interconnected through a LAN (local area network), and particularly to a microcomputer reset apparatus and method for resetting the microcomputer when it suspends its operation.
2. Description of Related Art
FIG. 5 shows a configuration of a conventional microcomputer reset apparatus disclosed in Japanese patent application laid-open No. 4-33117/1992, for example. In FIG. 5, the reference numeral 1 designates an oscillator; 2 designates a clock generator connected with the oscillator 1 for generating a clock signal for driving a microcomputer 6; 3 designates a pulse generator for generating a pulse signal of a fixed period; 4 designates an 8-bit timer that increments its count value in response to pulses of the pulse signal supplied from the pulse generator 3, resets its count value in response to a reset pulse fed from the microcomputer 6, and produces an overflow signal when its count value reaches a predetermined value; 5 designates a reset signal generator for generating a reset signal in response to the overflow signal; and 6 designates the microcomputer that operates in synchronization with the clock signal, and is reset in response to the reset signal supplied from the reset signal generator 5.
FIG. 6 is a block diagram showing a configuration interconnecting a plurality of microcomputers 6 through a LAN, in which 7 designates a serial bus.
Next, the operation of the conventional microcomputer reset apparatus will be described.
The microcomputers 6 interconnected through the serial bus 7 can exchange data with any other microcomputers through the serial bus 7 if they have a communication function. However, if an accident like disconnection of the oscillator 1 takes place in one of the microcomputers 6 during its transmission of data, it halts its operation with supplying the serial bus 7 with a dominant level signal (H (high) level signal, for example), or a recessive level signal (L (low) level signal, for example).
If the microcomputer 6 halts its operation with outputting the L level signal, it will have little effect on the other microcomputers 6, enabling them to exchange data through the serial bus 7. On the contrary, if the microcomputer 6 halts its operation with outputting the H level signal, the communication from that time on becomes impossible because the signal level on the serial bus 7 is maintained at the H level and cannot be shifted to the L level, even if any other microcomputers 6 supply the serial bus 7 with the L level signal.
Therefore, if such an accident takes place, it is necessary for the microcomputer 6 to be reset so that the serial bus 7 is released from the state in which it is held by the H level signal. In view of this, the conventional microcomputer reset apparatus resets the microcomputer in the following procedure if such an accident takes place.
First, in the normal mode in which no accident like disconnection of the oscillator 1 occurs, the microcomputer 6 can operate in synchronization with the clock signal supplied from the clock generator 2. This enables the microcomputer 6 to regularly supply the 8-bit timer 4 with the reset pulse to reset it, which in turn prevents the 8-bit timer 4 from producing the overflow signal, and the reset signal generator 5 from supplying the microcomputer 6 with the reset signal.
In contrast with this, if an accident like disconnection of the oscillator 1 takes place, the clock generator 2 halts supplying the clock signal to the microcomputer 6. This will suspend the operation of the microcomputer 6, and hence it cannot supply the 8-bit timer 4 with the reset pulse. As a result, receiving the pulse signal from the pulse generator 3, the 8-bit timer 4 overflows, and supplies the reset signal generator 5 with the overflow signal. Thus, the reset signal generator 5 supplies the microcomputer 6 with the reset signal to reset it, thereby releasing the serial bus 7 from the state in which it is held by the H level signal.
With the foregoing configuration, the conventional microcomputer reset apparatus can reset the microcomputer 6 if its operation happens to be suspended by an accident like disconnection of the oscillator 1. The microcomputer 6, however, must regularly supply the 8-bit timer 4 with the reset pulse as long as it operates normally. This presents a problem of increasing its processing load.
Furthermore, depending on the processing of the microcomputer 6, even if the microcomputer 6 operates normally, a halt of the oscillator 1 can take place before the count value of the 8-bit timer 4 overflows. Depending on the signal level and timing of the halt, however, the microcomputer 6 continues to output the reset pulse. This presents another problem in that the reset signal generator 5 cannot produce the reset signal.
Still another problem arises in that quick processing steps cannot be taken after detecting the halt of the oscillator 1 because the reset pulse produced by the microcomputer 6 is used.